Design and Verification of APB Protocol using SV and UVM

 

Why APB?

APB might not be the fastest bus in the AMBA family, but its simplicity and low power make it ideal for connecting peripherals like UARTs, timers, and GPIOs. It’s also a perfect starting point for understanding bus protocols and synchronous digital communication.

 My Work

I designed an APB slave module in System Verilog (SV) and built a Universal Verification Methodology (UVM) testbench to verify it.
The UVM environment included standard components — driver, sequencer, monitor, agent, scoreboard, and environment — all working together to generate randomized and directed test scenarios.

The goal was to ensure that the APB slave:

• Followed correct read/write transaction timing

• Responded properly to wait states and error conditions

• Achieved high functional coverage

What I Learned

Working with UVM changed how I think about verification. It taught me the value of reusability, modularity, and scalability — three pillars of modern verification methodology.
I also gained hands-on experience in:

• Writing and debugging SystemVerilog testbenches

• Understanding signal-level timing in APB transactions

• Using assertions and coverage metrics to catch corner cases early

• Watching the simulation waveforms align perfectly after days of debugging was a moment of pure satisfaction!

   Results

  The design achieved 100% functional coverage and over 95% code coverage, proving that the testbench was both efficient and exhaustive.
  More importantly, this project gave me the confidence to take on more complex protocols like AHB and AXI in the future.

  Final Thoughts

  This journey wasn’t just about completing an academic project — it was about bridging theory with real-world VLSI design and verification.
  SystemVerilog and UVM are more than tools; they’re the language of modern chip design, and learning them has been one of the most rewarding parts of my M.Tech journey.