Design and Verification of APB Protocol using SV and UVM
Why APB? APB might not be the fastest bus in the AMBA family, but its simplicity and low power make it ideal for connecting peripherals like UARTs, timers, and GPIOs. It’s also a perfect starting point for understanding bus protocols and synchronous digital communication . My Work I designed an APB slave module in System Verilog (SV) and built a Universal Verification Methodology (UVM) testbench to verify it. The UVM environment included standard components — driver, sequencer, monitor, agent, scoreboard, and environment — all working together to generate randomized and directed test scenarios . The goal was to ensure that the APB slave: Followed correct read/write transaction timing Responded properly to wait states and error conditions Achieved high functional coverage What I Learned Working with UVM changed how I think about verification. It taught me the value of reusability , modularity, and scalability — three pillars of modern verific...